Design of Word Level Multiplication Algorithm on Reordered Normal Basis

Normal basis is widely used for representation of binary field elements Much attention has been paid to trade off between time and number of gates, but until little attention has been paid to the problem of connecting the gates in economical and regular way to minimize chip and chip area and design costs. Two new level high speed architectures, reordered normal basis type-I and reordered normal basis type-II for binary field multiplication are proposed. It allows the designer to trade off between area and speed. Optimal normal basis type-II is a special class of exhibiting very low multiplication complexity. Reordered normal basis is referred to as a certain permutation of optimal normal basis. One unique feature of the proposed architectures is that the critical path delay is independent of the number of words or the field size. This enables the proposed multipliers to operate at very high clock rates regardless of the number of words or the field size.